1. Field of the Invention
The present invention relates to an interface circuit such as a memory control device for controlling access to a memory device, and in particular to a bus interface circuit for rapidly taking in data in synchronization with a clock signal.
2. Description of the Background Art
FIG. 78 shows an example of a structure of a conventional data processing system. In FIG. 78, the conventional processing system includes a clock generator CG generating a system clock signal CLK, memory units MU0-MUn connected in parallel to a common bus CB and operating in synchronization with system clock signal CLK, a processor PC, such as a CPU (Central Processing Unit), for processing data stored in memory units MU0-MUn, and a memory controller MCR for transferring data requested of accessing by processor PC between memory units MU0-MUn and processor PC. Memory controller MCR operates in synchronization with system clock signal CLK as well.
In such processing system, for achieving fast data processing, a system clock rate has been increased, and a fast bus interface has been defined for fast data transfer via the common bus CB between memory controller MCR and memory units MU0-MUm. As typical examples of such a fast interface, there are an interface of DDR (Double Data Rate) specification that data are transferred in synchronization with both the rising and falling edges of system clock signal CLK, and an interface of Rambus specification that the clock signal and data are transferred in the same direction. By utilizing such a fast interface, the efficiency of data transfer on common bus CB is improved, and a waiting time of processor PC is reduced so that the system performance is improved.
FIG. 79 shows a relationship in timing between the data and the system clock signal in the DDR mode. In the DDR mode, the data is sampled in synchronization with the rising edge and the falling edge of clock signal CLK. Data DO sampled at the rising edge of clock signal CLK has a set-up time, tsu, and a hold time, th, with respect to clock signal CLK. Likewise, data D1 sampled at the falling edge of clock signal CLK has set-up time, tsu, and hold time, th, with respect to the falling edge of clock signal CLK. The xe2x80x9csamplingxe2x80x9d means the timing at which memory controller MCR takes in the data, or the operation of taking the data into the memory unit.
Usually, data read from memory units MU0-MUn is transferred in synchronization with clock signal CLK. As clock signal CLK becomes faster and a cycle time T thereof becomes shorter, the set-up time, tsu, and hold time, th, of data D also become shorter. When clock signal CLK has a duty ratio of 50, a sum of set-up time, tsu, and hold time, th, can take the value of up to T/2. For example, if clock signal CLK has a frequency of 100 MHz, clock signal CLK has a period T of 10 ns (nano seconds) so that the set-up time, tsu, and hold time, th, can take the values of up to 5 ns. However, these specification values are of the order of pico-seconds. For ensuring such small specification values of the short set-up time and hold time, it is necessary to determine whether the specification values are accurately satisfied or not, and an expensive tester is required for such determination, resulting in increased cost of the memory unit.
According to the interface of the Rambus specification, the width and the data transfer rate of the data bus are fixedly determined. Therefore, a system designer cannot freely determine the transfer rate and the data bus width so that flexibility in design is considerably low.
Where memory controller MCR and memory units MU0-MUn as shown in FIG. 78 are assembled on-board, the impedance of common bus CB (data bus) changes in accordance with the number of on-board memory units, and may also change due to variations in arrangement of on-board wiring lines. If such changes occur in impedance of the common bus (data bus), no timing margin is present in receiving the data by memory controller MCR even if the set-up time and the hold time are set to the values within the specification values, respectively. Due to such less timing margin, it may be impossible to take in accurate data in many cases. As clock signal CLK becomes faster, an eye pattern (effective data period) of data D becomes shorter.
Therefore, as shown in FIG. 79, failures occur in the set-up margin and the hold margin for data when variations in propagation delay occur among the memory units in data transfer. For matching the impedances of the on-board wiring lines with each other, if wiring lines of equal lengths may be arranged between the memory units and the memory controller, the board must have a multi-layered structure, and the wiring must be made in a three-dimensional structure so that the circuit-board becomes expensive.
FIG. 80 schematically illustrates a timing relationship of data transfer between memory controller MCR and memory unit MU in the memory system shown in FIG. 78. In FIG. 80, each of memory controller MCR and memory unit MU includes a delayed locked loop (DLL) for generating an internal clock signal in accordance with the clock signal sent from clock generator CG. The clock signal generated by clock generator CG is transmitted as a clock signal Cy to memory controller MCR, and to memory unit MU as a clock signal Ct with a delay by a period Tskew due to a propagation delay on the clock signal line.
In memory unit MU, an output circuit outputs data Dt in accordance with the internal clock signal from DLL. Memory unit MU outputs data Dt from its output circuit with a delay of time Tt relative to the rising of the internal clock signal from DLL. Data Dt from memory unit MU reaches memory controller MCR after elapsing of a propagation delay time Tf. In memory controller MCR, a register takes in supplied data Dr in accordance with the internal clock signal generated from its internal DLL. When the register takes in data Dr that is sent from memory unit MU and arrives at memory controller MCR, the data is sampled into the register upon elapsing of set-up time Ts.
FIG. 81 is a signal waveform diagram representing operations of the system shown in FIG. 80. The clock signal generated from clock generator CG has a cycle period of Tcycle. Memory unit MU outputs effective data in accordance with clock signal Ct with a delay of time Tt. Data Dt from memory unit MU arrives at memory controller MCR via the data bus after time Tf. Data Dr arriving at memory controller MCR is sampled into the register in accordance with clock signal Cr upon elapsing of set-up time Ts.
Therefore, the propagation time Tf changes in accordance with the wiring length between memory unit MU and memory controller MCR. Propagation delay Tskew of the clock signal changes in accordance with the distance between clock generator CG and memory unit MU as well. Therefore, even with the DLL for outputting data Dt from memory unit MU in synchronization with the clock signal, set-up time Ts differs for a different length of the path from the output circuit of memory unit MU to the register of memory controller MCR. Thus, the timing margin for taking in the data becomes inadequate, and the memory system capable of accurate data transfer cannot be achieved.
In the structure with the memory modules assembled on-board, the impedance of the data bus locally changes depending on the number of the on-board memory modules. Therefore, it is extremely difficult to make a propagation delay on a signal transfer path, which extends from the clock generator through the memory module, data line and input pad to the register (receiver) of the controller, equal for all the memory modules (memory chips). Accordingly, it is difficult to achieve the on-board memory system, in which fast and accurate data transfer can be achieved under fast operation environments.
As shown in FIG. 80, memory unit MU is configured to output the data, synchronized in phase with clock signal CLK as much as possible, by using DLL for reducing the delay with respect to the supplied clock signal. However, provision of such DLL in memory unit MU increases the chip area of memory unit MU as well as power consumption, and in addition, the memory unit becomes expensive due to increase in chip area.
The following problems arise if the margin for data take-in timing at the memory controller changes in accordance with the position/number of the chips or modules in an on-board system. Specifically, if an error occurs in the data taken by the memory controller, it is difficult to determine whether the cause of this error is present in the data transfer path itself or in the memory unit (or chip). Thus, it is difficult to detect and eliminate the cause of error at the board level.
Further, in a multi-processor system in which a plurality of processors (CPUs) are connected in parallel to a data bus and access memory devices via a memory controller, such system is configured on-board. When data transfer is performed using a fast clock signal close to, e.g., 1 GHz in such on-board multi-processor system, margins of the set-up time and hold time for data sampling become extremely small and data cannot be transferred fast and accurately, resulting in a problem similar to that of the memory system already described above.
A similar problem occurs in a multiprocessor system, in which a plurality of processors are coupled in parallel to a common data bus, and access a common memory without control of a memory controller. Particularly, in the case where the system is expanded so that the number of processors increases or an impedance of the data bus increases, a skew of data with respect to a clock signal changes to impair the reliability of the system, resulting in low expandability of the system.
An object of the invention is to provide an interface circuit, which can accurately transfer data to any one of semiconductor devices in a system.
Another object of the invention is to provide an interface circuit, which can implement an on-board system allowing fast and accurate data transfer.
Still another object of the invention is to provide an interface circuit, which can ensure a sufficient set-up time and a sufficient hold time of data for each of on-board units when assembled on-board.
Yet another object of the invention is to provide an interface circuit, which can rapidly and accurately transfer data without increasing a cost of units in a system.
Further another object of the invention is to provide an interface circuit, which allows accurate identification of a cause of error even at the on-board level.
A further object of the invention is to provide an interface circuit for achieving an inexpensive system allowing fast and accurate data transfer regardless of the structure of the on-board system.
A particular object of the invention is to provide an inexpensive memory control device capable of fast and accurate data transfer.
An interface circuit according to the invention includes: production/storage circuitry for detecting a point of change in data on a data line, producing effective window information indicating an effective period of the data in accordance with a result of the detection, and storing the effective window information; strobe timing determining circuitry for determining a strobe timing for taking in data on the data line in accordance with the effective window information stored in the production/storage circuitry; and clock producing circuitry for producing a clock signal for taking in the data in accordance with the strobe timing determined by the strobe timing determining circuitry.
An interface circuit according to another aspect of the present invention includes: transition point detecting circuitry for detecting a point of transition in data on a data line; producing circuitry for producing effective window information indicating an effective period of the data in accordance with a transition point detected by the transition point detecting circuitry; determining circuitry for determining whether a width of the effective window satisfies a first condition; and storage circuitry for storing an address and a data pattern of the data when the determining circuitry determines that the first condition is satisfied.
An interface circuit according to still another aspect of the present invention includes: effective window extracting circuitry for detecting a point of change in data on a data line, and producing an effective window signal indicating an effective period of the data in accordance with a result of the detection; effective window width detecting circuitry for detecting an effective period width of the effective window signal using a reference clock signal, and storing a result of the detection; strobe timing storing circuitry for determining a strobe timing for the data on the data line from the effective window width information detected by the effective window width detecting circuitry, and storing the determined strobe timing; and strobe signal producing circuitry for producing a strobe signal for the data on the data line in accordance with the strobe timing stored in the strobe timing storing circuitry.
In the interface circuit, the effective window width of the data on the data line is detected, and the strobe timing for the data is determined in accordance with the detected effective window. Thereby, data strobe (sampling) can be performed at the optimum timing for the data on the data line. Even if a system constituent unit such as a memory device is assembled on a board and an impedance of a data transfer path changes in accordance with a system structure, the data can be accurately taken in.
When a detected effective window width does not satisfy predetermined conditions, conditions that would reduce the set-up/hold margins can be detected, so that the system can be made stable. By storing the pattern and address of the data when the margin is reduced, it can be determined whether the cause of failure is present in the data transfer device or on the data transfer path. When the cause of failure concentrates in the addresses of a specific memory chip, it can be determined that the cause of failure is present in that memory device (chip).
The foregoing and other objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings.